Towards a Strongly Fault Tolerant VLSI Processor Array
نویسنده
چکیده
In this paper a novel methodology to achieve fault tolerance in VLSI Array Processors is proposed. A “Fence” based approach is adopted in which the logic array is partitioned and spares are distributed along the boundary of the active array. The emulator as in conventional fault tolerance techniques takes care of fault mapping and reconfiguration. The latency, reconfiguration interconnect length and fault coverage issues, which are critical areas in VLSI Arrays, are discussed in detail.
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